1. Field of the Invention
The present invention relates to a semiconductor device having a polycide wiring layer in which a high melting point metal silicide layer is laminated on a polysilicon layer. More particularly, the present invention relates to a semiconductor device and a method of manufacturing the same, in which a wiring layer resistance of a polycide wiring layer is reduced for realization of fine patterns and high speed operation in the semiconductor device.
2. Description of the Related Art
With the high integration in a semiconductor device, it is aimed for a wiring layer between semiconductor elements or between the element and an electrode to have a fine and thin structure. For example, it is required to reduce the wiring layer width from the range of 200 to 250 nm to the range of 40 to 100 nm. Therefore, the increase of wiring resistance with the formation of the fine and thin wiring layer can not be ignored, and the decrease of the wiring layer resistance is required.
For example, when the wiring layer is applied to a word line of a semiconductor memory device, the access time of the memory device becomes long, if the wiring layer resistance is large. For this reason, the length of the word line can not be made longer than a predetermined value. As a result, the number of memory elements connectable with the word line can not be increased.
In order to solve the above problem, one word line is divided into a plurality of blocks, and a word line drive signal is supplied to the word line in each block through a buffer. However, in this method, there is a problem in that the memory chip size becomes large.
In order to achieve the reduction of the wiring layer resistance, it could be considered that metal, especially, high melting point metal is used as a material of the wiring layer. However, this technique can not be applied, when it is necessary to use polysilicon as the wiring layer material, like the wiring layer used as a gate electrode in a MOS transistor of the semiconductor device. Therefore, as one approach to make the wiring layer resistance of the polysilicon layer low, a polycide wiring layer is conventionally proposed.
The polycide wiring layer structure is shown in FIGS. 1A and 1B as a plan view and a cross sectional view, respectively. A polysilicon layer 204 is formed above a silicon substrate 201 on which a trench separation insulating film 202 and a gate insulating film 203 have been formed. A high melting point metal silicide 205 is laminated on the polysilicon layer 204. The polysilicon layer 204 and the high melting point metal silicide layer 205 are patterned into a predetermined pattern to form a polycide wiring layer 206. Thus, it is realized to make the wiring layer resistance low by use of a low sheet resistance of the high melting point metal silicide.
In such a polycide wiring layer, impurity ions, e.g., phosphorus ions are doped into the polysilicon 204 to realize the low resistance of the polysilicon 204. Also, the high melting point metal silicide layer 205 is formed by a CVD method. The high melting point metal silicide is composed of a lot of needle-shape crystals formed on the polysilicon surface on the formation of the high melting point metal silicide layer 205. A thermal annealing process is applied to the needle-shape crystals such that the crystals grow. Thus, grains or particles 205G with a required grain diameter are obtained. The polycide layer formed in this way is etched and patterned into a requested pattern using the photolithography technique, so that the polycide wiring layer 206 is completed.
By the way, the inventor studied such a polycide wiring layer. Consequently, it was discovered that the polycide wiring layer was not made low in resistance. The inventor paid attention to tungsten silicide (WSi) as the high melting point metal silicide, especially, the grains of tungsten silicide and observed them with an electron microscope. As the result of observation, the grain size or grain diameter of the grain was small rather than the film thickness of the WSi layer and the film width of the WSi layer. Also, the grains were formed in the state in which the grains were arranged in the film thickness direction of the WSi layer and the width direction of the WSi layer.
That is, the composition ratio of tungsten (W) and silicon (Si) in the formation of the WSi layer would be as large as 1:2.5, from the condition in the formation of the WSi layer. Also, a thermal annealing process after the formation of the WSi layer was carried out under the condition of the temperature equal to or lower than 900.degree. C. and annealing time of about 60 minutes. Therefore, it is inferred that Si atoms are deposited in the boundary between the grains, and the Si atoms function to hinder the growth of the grain.
Therefore, in an example shown in FIGS. 1A and 1B, Si atoms are deposited in the interface 205B between the grains 205G and the deposited Si atoms function to obstruct current flow between the grains. As a result, the sheet resistance of WSi layer becomes large. Also, when the polycide wiring layer is patterned, the wiring layer has the high resistance. It should be noted that the grain size or diameter means a maximum of the grain diameters in the present invention.
It should be noted that it is described in Japanese Laid Open Patent Application (JP-A-Heisei 7-283217) that the wiring layer resistance increases when the wiring layer has the width smaller than the grain size of titanium silicide (TiSi) in a titanium silicide layer. This does not correspond to the above studying by the inventor. This would be because of the difference between the reference and the present invention in manufacturing method. That is, in the reference, a thermal annealing process is carried out to form the TiSi layer after a titanium layer is deposited on a polysilicon layer. On the other hand, in the present invention, the WSi layer is formed on the polysilicon layer by the CVD method, to be described later.
Regardless of the cause, when the WSi grain size is smaller than the width and film thickness of the wiring layer, it is difficult to reduce the wiring layer resistance, as described above. Also, when the WSi layer is formed using a sputtering method, the grain diameter of the WSi grain is small. In order to increase the grain diameter of the WSi grain, it is necessary to perform the annealing process at a high temperature for a long time. However, when a gate wiring layer of the semiconductor device is formed of WSi, it is not possible to perform the annealing process for the long time, since the annealing process affects the diffusion layers of the source and drain.